1. Field of the Invention
The present invention relates to a data processing device (microprocessing unit), more particularly, to a data processing device for constituting a data processing system (computer system) by a plurality of data processing devices.
2. Description of the Related Art
Recently, a computer system (data processing system) having a plurality of microprocessing units (data processing devices) and a single main memory, which are connected by a system bus, have been provided. In the data processing device constituting such a computer system, buffers for copying a part of the contents of the main memory are provided in the microprocessing unit, as high speed data access in the main memory is required in accordance with the requirement of high speed operation in recent computer systems. In the microprocessing unit, when renewing the main memory, the contents of instruction data or operand data stored in the buffers are renewed or invalidated.
Namely, in the microprocessing unit, for example, when renewing the main memory by an internal operation, exclusive internal busses are provided for both the buffer storing the instruction data and another buffer storing the operand data, respectively, so that a renewal operation or invalidation operation in the buffers can be carried out.
As described above, in the conventional data processing system having a plurality of data processing devices (microprocessing units) for use as a computer system, a buffer (instruction cache memory) for storing instruction data and another buffer (operand cache memory) for storing operand data respectively have the exclusive internal busses (or the exclusive internal bus lines), whereby renewing or invalidating of the data within the buffers is carried out. In the same manner as described above, when renewing the contents of the main memory by another microprocessing unit, the data stored in the buffers in each microprocessing unit should be also required to be renewed or invalidated.
Therefore, controlling processes for buffers in the plural microprocessing units become complicated. Additionally, the exclusive busses should be provided for both buffers (instruction cache memory and operand cache memory), and thus the number of the internal bus lines in each of the microprocessing units becomes increased. Note, this essentially prevents the microprocessing unit or the computer system from realization of high speed operation and large scale integration. Furthermore, it is difficult to maintain consistency of the contents in the internal buffer and the main memory disposed in the plural microprocessing units.
In the conventional computer system comprising a plurality of data processing devices (microprocessing units), a number of exclusive use busses are required to be connected for arranging the buffers in each of the data processing devices. Consequently, a high speed operation and a large scale integration in the data processing device are prevented, and a consistency of contents in the internal buffers included in each of the plural data processing devices and the main memory cannot be practically maintained, and the control of the data processing device or the data processing system becomes complicated.